This invention relates to an electronic timepiece, and more particularly to an improved counter circuit which generates a quick advance signal required for time-setting in an electronic timepiece.
In a known type of electronic timepiece, the output of a quartz oscillator, having a predetermined frequency of 128 Hz, is introduced to a first frequency--dividing circuit to obtain a signal of 1 Hz thereby providing a "second" signal. Then the "second" signal thus obtained is counted by a "second" counter, i.e. a sexagesimal counter to obtain a "minute" signal, which in turn is fed to a liquid crystal or LED (light-emitting diode) display element through a decoder to indicate a time value, while the display element is driven according to a signal of a frequency of 32 Hz which has been obtained by dividing the frequency of 128 Hz, thereby effecting the digital time display.
For the time-setting of an electronic timepiece, two switch elements and a second frequency-dividing circuit are conventionally used therein. The first frequency-dividing circuit and the "second" counter are held inactive by closing one of the switch elements, while an output signal of the second frequency-dividing circuit, such as 1 Hz, is sent to the display element as a quick advance signal for setting the time by closing the other switch element. Therefore, the display element is driven by the quick advance signal of 1 Hz during the closed state of the second switch. Accordingly, the displayed minute or hour value advances at a 1 Hz rate from the initially indicated time value during the close-state of the second switch. When the display element indicates the time value at which the timepiece is to be set which passes in little real time, the second switch is turned off to prevent the generation of the quick advance signal. Then, the displayed time maintains the time value at the moment when the second switch is turned off. Thereafter, when the displayed time value is coincident with the real time, the first frequency-dividing circuit and the "second" counter are released from their reset condition by closing the first switch to thereby allow the counter to carry out normal time counting. The time-setting is completed in this manner.
However, in such a method for setting the time, the second frequency-dividing circuit adapted to generate the quick advance signal is necessary, so that an increase in the number of components of the circuit results. With the recent rapid development of integrated circuit technology, a reduction in the number of circuit components is desired by integrated circuit users.
It is accordingly a principal object of the present invention to provide an electronic timepiece which permits accurate time-setting, without providing an additional frequency-dividing circuit for use in generating a quick advance signal.